In recent years, SiC has attracted attention as a material of power devices that can provide a high breakdown field intensity. SiC semiconductor devices can be used in controlling high current because the SiC semiconductor devices have high field intensity. Therefore, SiC is expected to be applied in control of motors for hybrid cars.
When such SiC semiconductor devices are manufactured, a SiC single crystal wafer is used or a SiC single crystal layer doped with impurities is grown on a SiC single crystal substrate. At this time, for example, to obtain an n-type SiC single crystal having low resistance, nitrogen is required to be doped heavily as an n-type dopant. Specifically, a specific resistance demanded for devices is a few mΩcm and nitrogen should be doped heavily to reach this value.
However, it is confirmed that when nitrogen is doped to a SiC single crystal to reduce a resistance, stacking faults are generated easily if a concentration of nitrogen is 2×1019 cm−3 or higher. In a case where nitrogen is doped at 2×1019 cm−3, the specific resistance of a device is about 10 mΩcm and is a few times higher than the specific resistance demanded for devices. The specific resistance of devices decreases by doping more nitrogen, however, stacking faults increase substantially to about 800 to 1000 cm−1. The stacking faults become a leak current source or a resistance component in the manufactured devices and cause a negative effect on electric characteristics of the devices, so it is not just a matter of doping nitrogen.
JP-A-2008-290898 (corresponding to US 2010/0080956 A1) discloses a method to reduce generation of stacking faults during a heat treatment of a SiC single crystal substrate having low resistance. Specifically, 90% or greater of the whole surface of the SiC single crystal substrate is covered by a SiC single crystal plane having surface roughness (Ra) of 1.9 nm or less. Stacking faults are generated during the heat treatment which is performed in a case where a concentration of impurities is increased to reduce the resistance. The generated amount of stacking faults increases with an increase in the surface roughness. Therefore, in order to inhibit an increase in the generated amount of stacking faults, the surface of the SiC single crystal substrate is covered by a SiC single crystal plane having a small surface roughness so that a crystal defect is difficult to generate.
JP-A-10-017399 suggests a manufacturing method of 6H—SiC single crystal in which generation of a micropipe defect is prevented and the amount of stacking faults is small. Specifically, in a sublimation recrystallization method, a plane of a 6H—SiC that is inclined at an angle within ±30 degrees from a (11-20) plane toward a (0001) plane and is inclined at an angle within ±10 degrees from the (11-20) plane toward a (10-10) plane is used as a seed crystal substrate.
Although JP-A-2008-290898 suggests the method for inhibiting generation of stacking faults during the heat treatment, stacking faults are already generated during doping a great amount of nitrogen prior to the heat treatment. Therefore, the method has no effects unless the stacking faults are inhibited from a step of doping. In JP-A-10-017399, SiC of a specific polymorphism having a small amount of stacking faults is manufactured by using a specific plane direction as a growth face. However, the direction of the growth face is specified and the polymorphism of the manufactured SiC is also specified. Therefore, SiC single crystal having a small amount of stacking faults can be manufactured only in a limited way. In addition, it is not clear whether the generated amount of stacking faults can be reduced to a level that the stacking faults do not cause negative effects on electric characteristics of devices in a case where the doped amount is increased to reduce the resistance. Accordingly, a manufacturing method to reduce a specific resistance and to reduce generation of stacking faults is required.